The present disclosure relates to memory devices. More particularly, the disclosure relates to magnetic memory devices having improved switching characteristics.
Magnetic memory devices, such as magnetic random access memory (MRAM) devices, are non-volatile semiconductor devices that can be used to store data. An example of one such device 100 is illustrated in FIG. 1. As shown in this figure, the magnetic memory device 100 comprises a plurality of memory cells 102 that are arranged in a two-dimensional array (only a portion of the array shown in FIG. 1). The magnetic memory device 100 also comprises a plurality of column conductors 104 and row conductors 106 that are electrically coupled to the memory cells 102. Specifically, each memory cell 102 is connected to a column conductor 104 and a row conductor 106 at a cross-point of the conductors. Additionally, the magnetic memory device 100 includes column and row control circuits 108 and 110 which control switching for the various column and row conductors 104 and 106, respectively.
FIG. 2 provides a detailed view of a single memory cell 102 and its connection to its associated column and row conductor 104 and 106. As is evident from FIG. 2, each memory cell 102 typically comprises two magnetic layers 200 and 202 that are separated by a thin insulating layer 204. One of the magnetic layers (e.g., the bottom magnetic layer 202) has a fixed or xe2x80x9cpinnedxe2x80x9d magnetic orientation, while the other magnetic layer (e.g., the top magnetic layer 200) has a xe2x80x9cfreexe2x80x9d magnetic orientation that can be toggled from an orientation in which it is aligned with the orientation of the fixed magnetic layer to an orientation in which it opposes the orientation of the fixed magnetic layer. The former state is called the xe2x80x9cparallelxe2x80x9d state and the latter state is called the xe2x80x9canti-parallelxe2x80x9d state. Typically, the orientation of magnetization in the free layer (also referred to as the data layer or the storage layer) is aligned along its xe2x80x9ceasyxe2x80x9d axis.
The two different memory cell states can be used to record data due to their disparate effect on resistance of the memory cell 102. Specifically, the memory cell 102 has a relatively small resistance when in the parallel state, but has a relatively high resistance when in the anti-parallel state. The parallel state can be designated as representing a logic value xe2x80x9c1xe2x80x9d while the anti-parallel state can be designated as representing a logic value xe2x80x9c0xe2x80x9d or vice versa. In such a scheme, the magnetic memory device 100 can be written to by changing the magnetic orientation of the free layer of selected memory cells 102.
The control circuits 108 and 110 (FIG. 1) are used to facilitate selection of any given memory cell 102 during reading and writing. Normally, these circuits 108, 110 include a plurality of switches, for instance transistors, that are used to apply voltage and current to the selected conductors.
A memory cell 102 is usually written to a desired logic state by applying external magnetic fields that rotate the orientation of magnetization of its free layer. Typically, the external magnetic fields are applied by delivering current through both conductors 104, 106 associated with the selected memory cell 102 through use of the control circuits 108, 110. In particular, with reference to FIG. 2, the write current flowing through the column conductor 104, IYW, generates a write magnetic field along the X direction, HXW, and the write current flowing through the row conductor 106, IXW, generates a write magnetic field along the Y direction, HYW. These external magnetic fields, HXW and HYW, in combination flip the orientation of magnetization of the free layer along its easy axis to either the parallel or anti-parallel orientation.
With this writing scheme, only the selected memory cell 102 receives both HXW and HYW. The other memory cells 102 coupled to the particular conductors 104, 106 used to flip the selected memory cell only receive a single magnetic field (either HXW or HYW). In that they only receive one of the two magnetic fields, these other memory cells 102 are said to be xe2x80x9chalf-selected.xe2x80x9d The magnitudes of the applied magnetic fields are preferably chosen to be high enough so that the selected memory cell 102 switches its logic state, but low enough so that the half-selected memory cells do not switch their states.
The above-described switching characteristics are illustrated in FIG. 3, which provides an example switching curve 300 for a memory cell. In the graph, the X axis represents magnetic field in the X direction, HX, and the Y axis represents the magnetic field in the Y direction, HY. Switching occurs when the memory cell receives a field that extends to or beyond the switching curve 300. Therefore, the switching curve represents the threshold magnetic field that is required to switch a memory cell. When a given X direction write field, HXW, and a given Y direction write field HYX are applied to the selected memory cell, a resultant field, HR, is produced that reaches or exceeds the switching curve 300.
As indicated in FIG. 3, the switching curve crosses the X axis at the magnetic coercivity point, Hc, and runs asymptotically along the Y axis in both the positive and negative directions. In prior solutions, this configuration was considered ideal in that half-selected memory cells that only receive HYW can never switch and half-selected memory cells that only receive HXW will not switch unless HXW is very large. This latter phenomenon provides a margin, known as the half-select margin, between the applied X direction field (HXW) and that required to switch the memory cell when no Y direction field is applied.
Unfortunately, manufacturing variation among memory cells can skew the switching curve and therefore increase the likelihood of half-select switching, i.e. unintended switching of a half-selected memory cell. For example, manufacturing variation in the various dimensions or shapes of the memory cells may increase the likelihood of half-select switching. In addition, variation in the thickness or the crystalline anisotropy of the memory cell free layers may increase the likelihood of half-select switching. Such manufacturing variation decreases the yield in manufacturing processes for magnetic memory devices and reduces their reliability.
FIG. 4 illustrates an example of a switching curve 400 that may result from undesired manufacturing variation. As indicated in this figure, the magnitude of the X direction magnetic field required to switch the selected memory cell is very close to that which would be required to switch a half-selected memory cell that only receives the X direction magnetic field. Hence, the half-select margin for such a memory cell is small, thereby making half-select switching more likely.
From the above, it can be appreciated that it would be desirable to have magnetic memory devices that having improved switching characteristics such that half-select switching can be reduced.
The present disclosure relates to a magnetic memory device. In one embodiment, the device comprises a memory cell having an easy axis aligned along a first direction, the memory cell being configured so as to be most easily switched from one logic state to another when only receiving a magnetic field along the first direction, and a magnetic biasing element associated with the memory cell, the magnetic biasing element having a magnetic orientation aligned along a second direction different from the first direction.
With such a magnetic memory device, writing can be accomplished by applying a magnetic bias field to the memory cell, applying a first write magnetic field substantially equal in magnitude and opposite in direction to the magnetic bias field to negate the magnetic bias field, and applying a second write magnetic field in a direction different from the magnetic bias field and the first write field, the second write magnetic field having a magnitude sufficient to independently switch a logic state of the memory cell when the magnetic bias field is negated.